The short version
- 1Every GPU added to an AI cluster pulls in more optical interconnect. The hard parts don't scale at the same rate.
- 2The binding constraint is the EML laser — not the GPU, not the GaN. A handful of firms can make it, and NVIDIA has largely bought out their capacity.
- 3Three compound semiconductors gate everything: InP (the optical signal), GaN and SiC (the power to run it).
- 4CPO — putting the optics on the same chip as the processor — is the architecture that breaks the copper wall. It's where the next decade of margin sits.
Six stages, upstream to AI
Data moves from raw substrates to a finished AI cluster through six stages. Value — and scarcity — concentrate at the laser and the packaging steps, not the ends.
The real bottleneck is the EML laser
Two laser types feed AI optics. They could not be more different in how scarce they are. The EML (electro-absorption modulated laser) is the physical-layer wall for 800G and 1.6T modules. The VCSEL is plentiful and is not the constraint.
| EML — the hard bottleneck | VCSEL — not the bottleneck | |
|---|---|---|
| Where it's used | Long-haul, single-mode · 800G / 1.6T | Short-reach, multi-mode |
| Why it's hard | CW laser + modulator grown monolithically on InP — brutal yields | Made on GaAs, tested at wafer scale — high yield, low cost |
| Who can make it | ~5 firms: Broadcom, Lumentum, Coherent, Mitsubishi, Sumitomo | Many, including consumer-sensor makers |
| Supply state | ~30% gap even after expansion; NVIDIA pre-bought much of it | Healthy; single-channel 200G already shipping |
The shortage runs upstream, too: EML output is throttled by an InP substrate shortage, where AXT's backlog is at record highs. Non-NVIDIA buyers are quoted lead times into 2027.
Three compound semiconductors gate it all
Silicon can't make an efficient laser. The optical era runs on three compound semiconductors instead — one for the signal, two for the power.
One line: InP carries the light; GaN and SiC carry the power. They're separate chains that converge at the AI cluster.
Grid-to-chip: the power wall
The industry's own framing has shifted. The bottleneck isn't only the GPU — it's the whole system: power, cooling, supply chain. An AI factory is a power-constrained machine. On the grid-to-chip path, GaN and SiC become the system-level constraint — substrate supply, packaging and thermal limits, and foundry process all bind at once.
This doesn't contradict the optical story; it's a different axis. On the signal path, the bottleneck is EML + InP. On power and cooling, it's GaN/SiC. Same AI map, two different chokepoints.
What CPO actually is
Three terms get used interchangeably. They're actually a hierarchy — a science, a hardware architecture, and a global system.
| What it is | Where it lives | |
|---|---|---|
| Photonics | The science of engineering light | Research, materials, components |
| CPO | A manufacturing architecture | Inside one chip / server box |
| Optical network | A large-scale comms system | Across buildings, cities, oceans |
Traditionally a processor sends an electrical signal across a copper board to a separate front-panel transceiver that converts it to light. At 200 Gbps and above, copper means heat, power draw, and signal loss. Co-packaged optics (CPO) integrates the transceiver directly onto the silicon next to the processor — data leaves as light immediately, cutting power use by up to ~50%.
That's why the giants are committing billions to the shift: NVIDIA is expanding optical-connection capacity with Corning and investing in component leaders like Coherent. Moving data with photons instead of electrons is the only way to keep global compute from grinding to a halt.
Who owns the chokepoints
Strip the full supplier table down to the names that actually gate each scarce step:
Where the basket points
The thesis is asymmetry: demand for AI compute pulls hardest on the steps the market under-owns — the EML laser, its InP feedstock, and the CPO integrators that replace copper with light. That's the spine of the Photonics basket.